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Satya Pandya

Junior IC Design Engineer specializing in ASIC/FPGA RTL design and verification

Western SemiconductorStony Brook UniversityTempe, AZ3 Years ExperienceIntern LevelWorks On-Site

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About

Engineer with 7 years of project experience who described owning a medical delivery UAV project from airfoil selection and stability analysis through CAD design, fabrication, flight testing, and post-launch iteration. Also led a master's thesis project end-to-end, including defining testing specs, coordinating with a specialized coating company, and driving improvements through feedback.

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Key Strengths

  • end-to-end UAV product development
  • aerodynamics and airfoil evaluation
  • hands-on prototyping and manufacturing
  • post-test iteration based on flight data
  • cross-functional collaboration with external partners
  • ownership of thesis-driven product testing project
  • practical problem-solving in weight distribution and stability

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Experience

IC Design InternWestern Semiconductor · Feb 2025 – Mar 2025internship
ASIC InternMIT Beaver Institute · Jun 2024 – Aug 2024internship
Systems EngineerTransUnion · Oct 2019 – Jul 2022

Education

Stony Brook Universitymaster, Electrical Engineering (2024)
GITAM Universitybachelor, Electronics and Communication Engineering (2018)

Skills

C++PythonLinuxGitMonitoringTroubleshootingFull-Stack DevelopmentSystemVerilogVerilogRTL DesignFunctional VerificationASIC DesignFPGA DesignObject-Oriented ProgrammingUVM

Languages

English

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Typically responds within 24 hours

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Hire with Reval

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Satya PandyaJunior IC Design Engineer specializing in ASIC/FPGA RTL design and verification