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Raja Thunga

Mid-level VLSI Physical Design Engineer specializing in advanced-node SoC timing closure

QorvoUniversity of North TexasDenton, TX4 Years ExperienceMid LevelWorks On-Site

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Experience

Physical Design EngineerQorvo, Inc. · Jan 2024 – Present
ASIC Physical Design EngineerSynapse Design Pvt. Ltd. · Jun 2021 – Aug 2022
Physical Design & STACadence Design Systems India Pvt. Ltd. · Mar 2020 – May 2021

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Education

University of North Texasmaster, Electrical Engineering (2024)
REVA Universitybachelor, Electronics and Communication Engineering (2021)

Skills

Root Cause AnalysisGitJenkinsCC++PythonRTL DesignASIC Design FlowFPGA Design FlowMicroarchitectureFunctional VerificationUVMSVASynthesisStatic Timing Analysis (STA)

Languages

English

Certifications

Certified VLSI Physical Design EngineerVLSI CAD Part 2: Layout

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Connect with Raja

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Typically responds within 24 hours

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Raja ThungaMid-level VLSI Physical Design Engineer specializing in advanced-node SoC timing closure