Raja Thunga

Mid-level VLSI Physical Design Engineer specializing in advanced-node SoC timing closure

Denton, TXPhysical Design Engineer4 years experienceMid-LevelSemiconductorsElectronic Design Automation (EDA)Technology

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Experience

Physical Design EngineerQorvo, Inc.

ASIC Physical Design EngineerSynapse Design Pvt. Ltd.

Physical Design & STACadence Design Systems India Pvt. Ltd.

Education

University of North Texasmaster, Electrical Engineering (2024)

REVA Universitybachelor, Electronics and Communication Engineering (2021)

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Languages

English

Skills

RTL DesignASIC Design FlowFPGA Design FlowMicroarchitectureFunctional VerificationUVMSVASynthesisStatic Timing Analysis (STA)Timing ClosureDesign for Testability (DFT)ATPGScan InsertionLow-Power DesignClock Domain Crossing (CDC)