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Antonio Hernandez Ruiz

Entry-Level Embedded/FPGA Engineer specializing in RTL design and verification

University of California, Santa CruzUC Santa Cruz2 Years ExperienceEntry LevelWorks On-Site

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Experience

Undergraduate Researcher, UCSCUniversity of California, Santa Cruz (UCSC) · Jan 2025 – Jun 2025
Intern|UCSC PPDOUniversity of California, Santa Cruz (UCSC) PPDO · Jan 2023 – Jun 2025internship

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Education

UC Santa Cruzbachelor, Computer Engineering (2025)

Skills

CC++PythonBashSQLLinuxGitData AnalysisVerilogFinite State Machine (FSM) DesignRTL DesignTestbench DevelopmentSelf-checking TestbenchesDigital Design VerificationTiming Closure

Languages

EnglishSpanish

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Connect with Antonio

Antonio already has a relationship with Reval, so a warm intro from us gets a much better response than cold outreach.

Typically responds within 24 hours

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Hire with Reval

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Antonio Hernandez RuizEntry-Level Embedded/FPGA Engineer specializing in RTL design and verification